ISCA-24 Advance Program
Conference at a Glance
Sunday, June 1
08:30-12:30 Tutorial T1: Arch. and Design Implications of Media processing
08:30-12:30 Tutorial T2: Parallel Processing Architectures Using PCs and Linux
13:30-17:30 Tutorial T3: Compiling and Executing Multiple Superscalar Threads
13:30-17:30 Tutorial T4: System Issues in Designing Parallel I/O Subsystems
08:30-17:30 Workshop W1: Performance Analysis and its Impact on Design
08:30-17:30 Workshop W2: Mixing Logic and DRAM: Chips that Compute and Remember
18:30-20:00 Welcoming Reception
Monday, June 2
09:00-09:30 Welcoming Remarks
09:30-10:30 Keynote Address: James E. Smith
11:00-12:30 Session 1a: Caching Techniques for ILP
11:00-12:30 Session 1b: Networks and Input/Output
12:30-14:00 Lunch - on your own
14:00-15:30 Session 2: Multiprocessors
16:00-17:30 Session 3: Memory System Design
21:00- Business Meeting
Tuesday, June 3
09:00-10:30 Session 4: Issues in Shared Memory Systems
11:00-12:30 Session 5a: Improving ILP
11:00-12:30 Session 5b: NUMA and COMA Architectures
12:30-14:00 Eckert-Mauchly Award Luncheon
14:00-15:30 Session 6: Prefetching and Prediction
15:30 Excursion
Wednesday, June 4
09:00-10:30 Session 7: Branch Prediction
11:00-12:30 Session 8: Managing the Memory Hierarchy and Memory Centric Arch.
12:30 End of ISCA'97 Conference
Conference in Detail
Sunday, June 1st 1997
Tutorials and Workshops
Tutorial T1
Speaker: Pradeep K. Dubey (IBM, T.J. Watson Research Center)
Tutorial T2
Speaker: Hank Dietz (Purdue University)
Tutorial T3
1:30-5:30 Compiling and Executing Multiple Superscalar Threads
Speakers: Alex Nicolau (University of California, Irvine)
Constantine D. Polychronopoulos (University of Illinois)
Tutorial T4
Speakers: Rajesh Bordawekar (California Institute of Technology)
Alok Choudhary (Northwestern University)
Workshop W1
8:30-5:30 Performance Analysis and its Impact on Design (PAID'97)
Organizers: Tom Conte (North Carolina State University)
Pradip Bose (IBM T. J. Watson Research Center)
The Advance Program is now available at:
PAID Advanced Program
Workshop W2
Organizers: David A. Patterson (University of California, Berkeley)
Michael D. Smith (Harvard University)
Monday, June 2nd 1997
9:00 Welcoming Remarks
Andrew R. Pleszkun, General Chair
Trevor Mudge, Program Chair
9:30 Keynote Speech
Amdahl's Law: Not Just an Equation
Postscript
James E. Smith
Dept. ECE, University of Wisconsin-Madison
10:30 Break
11:00 Caching Techniques for Instruction Level Parallelism
Concurrent with next session
Chair: Tom Conte, North Carolina State University
- Improving Superscalar Instruction Dispatch and Issue by Exploiting
Dynamic Code Sequences, Sriram Vajapeyam and Tulika Mitra,
Dept. Computer Science and
Automation, Indian Institute of Science
- Exploiting Instruction Level Parallelism in Processors by Caching
Scheduled Groups,
Ravi Nair and Martin E. Hopkins, IBM
T.J. Watson Research Center
- DAISY: Dynamic Compilation for 100% Architectural Compatibility,
Erik Altman and Kemal Ebcioglu, IBM T.J. Watson Research Center
11:00 Networks and Input/Output
Concurrent with previous session
Chair: Peter Chen, The University of Michigan
- On Deadlocks in Interconnection Networks, Timothy
Mark Pinkston and Sugath Warnakulasuriya,
University of Southern California.
- Implementing Multidestination Worms in Switch-Based Parallel
Systems: Architectural Alternatives and their Impact, Craig
B. Stunkel, IBM T. J. Watson Research Center, Rajeev Sivaram and
Dhabaleswar K. Panda, The Ohio State University
- Tolerating Multiple Failures in RAID Architectures with Optimal
Storage and Uniform Declustering,
Guillermo A. Alvarez, Walter A. Burkhard and Flaviu Cristian
Dept. of Computer Science and Engineering, University of
California, San Diego.
12:30 Lunch - on your own
2:00 Multiprocessors
Chair: David Wood, Computer Sciences Department, University of Wisconsin-Madison
- Hardware Fault Containment in Scalable Shared-Memory
Multiprocessors, Dan Teodosiu, Joel Baxter, Kinshuk Govil, John
Chapin*, Mendel Rosenblum and Mark Horowitz, Computer Systems
Laboratory Stanford University, * MIT Laboratory for Computer Science
- Effects of Communication Latency, Overhead and
Bandwidth in a Cluster Architecture, Richard P. Martin,
Amin M. Vahdat, David E. Culler and Thomas E. Anderson,
University of California-Berkeley
- The Mercury Interconnect Architecture: A Cost-effective
Infrastructure for High-performance Servers Wolf-Dietrich
Weber, Stephen Gold, Pat
Helland, Takeshi Shimizu, Thomas Wicki and Winfried Wilcke, HAL
Computer Systems.
3:30 Break
4:00 Memory System Design
Chair: Wen-mei Hwu, University of Illinois-Urbana Champaign
- The Design and Analysis of a Cache Architecture for
Texture Mapping, Ziyad Hakura and Anoop Gupta, Stanford
University.
- Designing High Bandwidth On-Chip Caches Kenneth Wilson and
Kunle Olukotun, Stanford University.
- Memory System Design Considerations in Dynamically-scheduled Processors,
Keith I. Farkas, Paul Chow, Norman P. Jouppi*, Zvonko Vranesic,
University of Toronto,
* Digital Equipment Corporation Western Research Lab
5:30 Dinner - on your own
9:00 Business meetings
Tuesday, June 3rd 1997
9:00 Issues in Shared Memory Systems
Timothy Mark Pinkston, University of Southern California
- The
Interaction of Software Prefetching with ILP Processors in Shared-Memory
Systems, Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi and
Sarita V. Adve, Rice University.
- VM-based Shared Memory on Low Latency, Remote Memory Access
Networks, Leonidas Kontothanassis*, Galen Hunt, Robert
Stets, Nikolaos Hardavellas, Michal Cierniak, Srinivasan Parthasarathy,
Wagner Meira, Jr., Sandhya Dwarkadas, and Michael L. Scott.
Dept. of Computer Science, University Rochester,
* DEC-Cambridge Research Lab
- Efficient Synchronization: Let Them Eat QOLB, Alain
Kägi, Doug Burger and James R. Goodman, Computer
Sciences Department, University of Wisconsin-Madison
10:30 Break
11:00 Improving Instruction Level Parallelism
Concurrent with next session
Chair: Dave Patterson, Univ. of California-Berkeley
- Dynamic Speculation and Synchronization of Data Dependences,
Andreas Moshovos, Scott E. Breach, T.N. Vijaykumar and Gurindar
S. Sohi, Computer Sciences Department, University of
Wisconsin-Madison
- Dynamic Instruction Reuse, Avinash Sodani and Gurindar S. Sohi,
Computer Sciences Department, University of Wisconsin-Madison
- Complexity-Effective Superscalar Processors, Subbarao Palacharla,
UW-Madison, Norman P. Jouppi, DEC-WRL, J. E. Smith, UW-Madison
11:00 NUMA and COMA Architectures
Concurrent with previous session
Chair: Per Stenstrom, Chalmers University
- Coherence Controller Architectures for SMP-based CC-NUMA
Multiprocessors, Maged M. Michael, University of
Rochester, Ashwini K. Nanda, Beng-Hong Lim, IBM T.J. Watson Research
Center, and Michael L. Scott, University of Rochester.
- Reactive NUMA: A Design for Unifying S-COMA and CC-NUMA,
Babak Falsafi and David A. Wood, Univ. of Wisconsin-Madison.
- The SGI Origin 2000: A CC-NUMA Highly Scalable Server, James
Laudon and Daniel Lenoski, Silicon Graphics.
12:30 Eckert-Mauchly Award Luncheon
Presented by Wen-mei Hwu, Chairman of the Eckert-Mauchly Award committee
Committee members
Forest Baskett, Silicon Graphics Inc.
Laxmi Bhuyan, Texas AM
David J. Kuck, Kuck & Associates, Inc.
Wen-mei Hwu, University of Illinois
Trevor Mudge, University of Michigan
Lionel Ni, Michigan State
2:00 Prefetching and Prediction
Chair: Joel Emer, Digital Equipment Corp.
- Prefetching Using Markov Predictors Dirk Grunwald
University of Colorado, and Douglas Joseph, IBM T.J. Watson Research Center
- Data Prefetching on the HP PA8000,
Vatsa Santhanam, Edward H. Gornish and Wei-Chung Hsu, Hewlett-Packard.
- Target Prediction for Indirect Jumps, Po-Yung Chang, Eric Hao,
Yale N. Patt, The University of Michigan
Wednesday, June 4rd 1997
9:00 Branch Prediction
Chair: David Nagle, Carnegie-Mellon University
- The Agree Predictor: A Mechanism for Reducing Negative Branch
History Interference, Eric Sprangle*, Robert Chappell, Mitch Alsup*,
Yale N. Patt, Univ. of Michigan, *Ross Technology
-
Trading Conflict and Capacity Aliasing in Conditional Branch
Predictors, Pierre Michaud (IRISA/INRIA), André Seznec
(IRISA/INRIA), Richard Uhlig (Intel Corporation)
- A Language for Describing Predictors and Its Application to Automatic
Synthesis, Joel Emer, DEC, and Nickolas Gloy, Harvard University.
10:30 Break
11:00 Managing the Memory Hierarchy and Memory-Centric Architectures
Chair: Mike Smith, Harvard University
- Run-Time Adaptive Cache Hierarchy Management via Reference
Analysis, Teresa L. Johnson and Wen-mei Hwu, Center for Reliable
and High-Performance Computing, University of Illinois, Urbana-Champaign
- The Energy Efficiency of IRAM Architectures, Richard Fromm,
Stylianos Perissakis, Neal Cardwell, Bruce McGaughy, Christoforos
Kozyrakis, David Patterson, Thomas Anderson and Kathy Yelick,
Univ. of California-Berkeley.
- DataScalar Architectures, Doug Burger, Stefanos
Kaxiras, James R. Goodman,
Computer Sciences Dept., University of Wisconsin-Madison
12:30 End of ISCA Conference
There are two workshops that may be of interest to conference
attendees. They are being held at the Oxford Hotel, 2 blocks away from
the conference hotel.
2:00 Academic Careers Workshop
The Computing Research Association's Academic Careers Workshop covers
the tenure process, networking with other researchers,
selecting and managing a research program, getting funding, and
time management/family issues. Its target audience is
faculty in the beginning years of their careers and senior graduate students
contemplating an academic career. This workshop ends at noon Thursday.
See the
workshop page
for more details, including how to register. (Organized by David A. Patterson.)
Thursday, June 5th 1997
2:00 Teaching in Computer Science and Engineering Workshop
The purpose of the Computing Research Association's Effective Teaching
in Computer Science and Engineering Workshop is to help
new faculty members teach more effectively. This highly interactive
workshop includes theoretical material on learning styles and
instructional objectives, and practical tips on effective lecturing,
creative problem-solving and collaborative learning.
This workshop ends at noon Friday.
See the
workshop page
for more details,
including how to register.
(Organized by Michael R. Williams.)