Krste Asanović, Publications by Year
Many of these papers are copyright of the respective journal or
conference organizing body. These online copies are provided for your
personal research use only.
2006
- Seongmoo Heo, Ronny Krashinsky, and Krste Asanović,
"Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy",
To appear, IEEE Transactions on VLSI Systems.
- Jessica Tseng and Krste Asanović,
"RingScalar: A Complexity-Effective Out-of-Order Superscalar
Microarchitecture", MIT CSAIL Technical Report MIT-CSAIL-TR-2006-066,
September 2006.
PDF
-
Krste Asanović, John Hennessy, David A. Patterson,
"Vector Processors", Appendix F in
Computer Architecture: A
Quantitative Approach, Fourth Edition,
Morgan Kaufman, ISBN 0-12-370490-1, September 2006.
-
Kenneth C. Barr and Krste Asanović,
"Energy-Aware Lossless Data Compression",
ACM Transactions on Computer Systems, 24(3):250-291, August 2006.
- David Patterson, Arvind, Krste Asanović, Derek Chiou, James
C. Hoe, Christoforos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan Rabaey,
and John Wawrzynek, "RAMP: Research Accelerator for Multiple
Processors", Hot Chips 18, Stanford, CA, August 2006.
PDF
- Vern Paxson, Krste Asanović, Sarang Dharmapurikar, John
W. Lockwood, Ruoming Pang, Robin Sommer, Nicholas C. Weaver,
"Rethinking Hardware Support for Network Analysis and Intrusion
Prevention", 1st Workshop on Hot Topics in Security
(HotSec'06), Vancouver, Canada, July 2006.
PDF
-
Mark Hampton and Krste Asanović, "Implementing Virtual Memory
in a Vector Processor with Software Restart Markers",
20th ACM International Conference on Supercomputing (ICS06),
Cairns, Australia, June 2006.
PDF
-
Jae W. Lee and Krste Asanović, "METERG: Measurement-Based
End-to-End Performance Estimation Technique in QoS-Capable
Multiprocessors", 12th IEEE Real-Time and Embedded
Technology and Applications Symposium (RTAS 2006), San Jose, CA,
April 2006.
PDF
-
Rose F. Liu and Krste Asanović, "Accelerating Architectural
Exploration Using Canonical Instruction Segments", IEEE
International Symposium on Performance Analysis of Systems and
Software (ISPASS-2006), Austin, TX, March 2006.
PDF
-
Kenneth C. Barr and Krste Asanović, "Branch Trace Compression
for Snapshot-Based Simulation", IEEE International Symposium on
Performance Analysis of Systems and Software (ISPASS-2006),
Austin, TX, March 2006. PDF
-
C. Scott Ananian, Krste Asanović, Bradley C. Kuszmaul, Charles E. Leiserson,
and Sean Lie,
"Unbounded Transactional Memory",
IEEE Micro Special Issue: Top Picks from
Computer Architecture Conferences, January/February 2006.
PDF
- Theses Supervised:
-
Kenneth C. Barr
"Summarizing Multiprocessor Program Execution with Versatile, Microarchitecture-Independent Snapshots"
Ph.D. Thesis, Massachusetts Institute of Technology, August 2006.
PDF
-
Jessica H. Tseng,
"Banked Microarchitectures for Complexity-Effective Superscalar
Microprocessors"
Ph.D. Thesis, Massachusetts Institute of Technology, May 2006.
PDF
-
Albert Ma,
"Circuits for High-Performance Low-Power VLSI Logic"
Ph.D. Thesis, Massachusetts Institute of Technology, May 2006.
PDF
-
Michael Zhang,
"Latency Reduction Techniques for Chip Multiprocessor Cache Systems"
Ph.D. Thesis, Massachusetts Institute of Technology, January 2006.
PDF
-
Seongmoo Heo,
"Optimal Digital System Design in Deep Submicron Technology"
Ph.D. Thesis, Massachusetts Institute of Technology, January 2006.
PDF
2005
-
Emmett Witchel, Junghwan Rhee, Krste Asanović,
"Mondrix: Memory Isolation for Linux using Mondriaan Memory
Protection", 20th ACM Symposium on Operating Systems
Principles (SOSP-20) Brighton, UK, October 2005.
PDF
- Michael Zhang and Krste Asanović, "Victim Migration: Dynamically
Adapting Between Private and Shared CMP Caches", MIT CSAIL Technical
Report, MIT-CSAIL-TR-2005-064, October 2005.
PDF
- Arvind, Krste Asanović, Derek Chiou, James C. Hoe, Christoforos
Kozyrakis, Shih-Lien Lu, Mark Oskin, David Patterson, Jan Rabaey, and
John Wawrzynek, "RAMP: Research Accelerator for Multiple Processors
- A Community Vision for a Shared Experimental Parallel HW/SW Platform",
UC Berkeley Technical Report UCB/CSD-05-1412, September 2005.
PDF
-
Heidi Pan, Krste Asanović, Robert Cohn, and Chi-Keung Luk,
"Controlling Program Execution through Binary Instrumentation",
Workshop on Binary Instrumentation and Applications
(WBIA-2005), at 14th International Conference on Parallel Architectures
and Compilation Techniques (PACT-14), St. Louis, MO, September
2005.
PDF
-
Seongmoo Heo and Krste Asanović, "Replacing Global Wires with an
On-Chip Network: A Power Analysis",
International Symposium on Low Power Electronics and
Design (ISLPED'05), San Diego, CA, August 2005.
PDF
-
Jessica H. Tseng and Krste Asanović,
"A Speculative Control Scheme for an Energy-Efficient Banked
Register File",
IEEE Transactions on Computers, 54(6):741-751, June 2005.
-
Michael Zhang and Krste Asanović, "Victim Replication: Maximizing
Capacity while Hiding Wire Delay in Tiled CMPs",
32nd International Symposium on Computer
Architecture (ISCA-32), Madison, WI, June 2005.
PDF
-
Kenneth C. Barr, Heidi Pan, Michael Zhang, and Krste Asanović,
"Accelerating Multiprocessor Simulation with a Memory Timestamp Record",
IEEE International Symposium on Performance Analysis of Systems
and Software (ISPASS-2005), Austin, TX, March 2005.
PDF
-
C. Scott Ananian, Krste Asanović, Bradley C. Kuszmaul, Charles E. Leiserson,
and Sean Lie,
"Unbounded Transactional Memory",
11th International Symposium on High Performance Computer
Architecture (HPCA-11), San Francisco, CA, February 2005.
PDF
Selected as one of IEEE Micro's "Top Picks from Computer Architecture
Conferences, 2005".
- Theses Supervised:
-
Steven Gerding, "The Extreme Benchmark Suite: Measuring
High-Performance Embedded Systems"
S.M. Thesis, Massachusetts Institute of Technology, September 2005.
PDF
-
Vimal Bhalodia, "SCALE DRAM Subsystem Power Analysis"
M.Eng. Thesis, Massachusetts Institute of Technology, September 2005.
PDF
-
Rose F. Liu, "AXCIS: Rapid Processor Architectural Exploration
using Canonical Instruction Segments"
M.Eng. Thesis, Massachusetts Institute of Technology, September 2005.
PDF
-
Elizabeth A. Basha, "Fast Fourier Transform on a 3D FPGA"
S.M. Thesis, Massachusetts Institute of Technology, September 2005.
PDF
2004
-
Christopher Batten, Ronny Krashinsky, Steven Gerding, and Krste Asanović,
"Cache Refill/Access Decoupling for Vector Machines",
37th International Symposium on Microarchitecture
(MICRO-37), Portland, OR, December 2004.
PDF
-
Ronny Krashinsky, Christopher Batten, Mark Hampton, Steven Gerding,
Brian Pharris, Jared Casper, and Krste Asanović,
"The Vector-Thread Architecture",
IEEE Micro Special Issue: Top Picks from
Computer Architecture Conferences, November/December 2004.
PDF
-
Seongmoo Heo and Krste Asanović,
"Power-Optimal Pipelining in Deep Submicron Technology",
International Symposium on Low Power Electronics and
Design (ISLPED'04), Newport Beach, CA, August 2004.
PDF
- Krste Asanović and Emmett Witchel, "System and technique
for fine-grained computer memory protection", US Patent, filed July 2004.
-
Seongmoo Heo and Krste Asanović,
"Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage
Reduction",
MIT LCS Technical Report, MIT-LCS-TR-957, July 2004.
PDF
-
Rodric M. Rabbah, Ian Bratt, Krste Asanović, and Anant Agarwal,
"Versatility and VersaBench: A New Metric and a Benchmark Suite for
Flexible Architectures",
MIT CSAIL Technical Memo, MIT-LCS-TM-646, June 2004.
PDF
-
Ronny Krashinsky, Christopher Batten, Mark Hampton, Steven Gerding,
Brian Pharris, Jared Casper, and Krste Asanović,
"The Vector-Thread Architecture",
31st International Symposium on Computer Architecture
(ISCA-31), Munich, Germany, June 2004.
PDF
Selected as one of IEEE Micro's "Top Picks from Computer Architecture
Conferences, 2004".
- Steven Miller, Martin Deneroff, Curt Schimmel, Krste
Asanović, Larry Rudolph, Charles Leiserson, Bradley Kuszmaul,
"System and method for performing memory operations in a computing
system", US Patent, filed April 2004.
- Theses Supervised:
-
Emmett Witchel, "Mondriaan Memory Protection"
Ph.D. Thesis, Massachusetts Institute of Technology, February 2004.
PDF
Received Honorable Mention, ACM Distinguished Dissertation
Awards, 2004.
Winner, George M. Sprowls Award for best Ph.D. thesis in Computer
Science, MIT, 2004.
-
Brian Pharris, "The SCALE DRAM Subsystem"
M.Eng. Thesis, Massachusetts Institute of Technology, May 2004.
PDF
-
Sean Lie, "Hardware Support for Unbounded Transactional Memory"
M.Eng. Thesis, Massachusetts Institute of Technology, May 2004.
PDF
-
Kelly Koskelin, "EProf: An Energy Profiler for the iPAQ"
M.Eng. Thesis, Massachusetts Institute of Technology, February 2004.
PDF
-
Aaron Mihalik, "VISTA: A Visualization Tool for Computer Architects"
M.Eng. Thesis, Massachusetts Institute of Technology, February 2004,
PDF
2003
-
Seongmoo Heo, Kenneth C. Barr, and Krste Asanović,
"Reducing Power Density through Activity Migration",
International Symposium on Low Power Electronics and
Design (ISLPED'03), Seoul, Korea, August 2003.
PDF
-
Jessica H. Tseng and Krste Asanović,
"Banked Multiported Register Files for High-Frequency Superscalar
Microprocessors",
30th International Symposium on Computer Architecture
(ISCA-30), San Diego, CA, June 2003.
PDF
-
Emmett Witchel and Krste Asanović,
"Hardware Works, Software Doesn't: Enforcing Modularity with
Mondriaan Memory Protection",
Ninth Workshop on Hot Topics in Operating Systems
(HotOS-IX), Lihue, HI, May 2003.
PDF
-
Kenneth C. Barr and Krste Asanović,
"Energy Aware Lossless Data Compression",
First International Conference on Mobile Systems,
Applications, and Services (MobiSys-2003) , San Francisco, CA, May 2003.
PDF
Winner, Best Paper Award, MobiSys 2003.
- Theses Supervised:
-
Tina Cheng, "Sieve: An XML-Based Structural Verilog Rules Check Tool"
M.Eng. Thesis, Massachusetts Institute of Technology, August 2003.
PDF
-
Regina Sam , "ZOOM: A Performance-Energy Cache Simulator"
M.Eng. Thesis, Massachusetts Institute of Technology, May 2003.
PDF
-
Sheetal Jain , "Low-Power Single-Precision IEEE Floating-Point Unit"
M.Eng. Thesis, Massachusetts Institute of Technology, May 2003.
PDF
-
Elina Kamenetskaya, "Video over IP: An Example Reconfigurable
Computing Application for a Handheld Device"
M.Eng. Thesis, Massachusetts Institute of Technology, May 2003.
PDF
2002
-
Krste Asanović, "Programmable Neurocomputing", in
The Handbook of Brain Theory and Neural Networks: Second Edition,
M. A. Arbib (Ed.), MIT Press, ISBN 0-262-01197-2, November 2002.
PDF
-
Emmett Witchel, Josh Cates, and Krste Asanović,
"Mondrian Memory Protection",
Tenth International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS-X) ,
San Jose, CA, October 2002.
PDF
-
Michael Zhang and Krste Asanović,
"Miss Tags for Fine-Grain CAM-Tag Cache Resizing",
International Symposium on Low Power Electronics and Design (ISLPED'02),
Monterey, CA, August 2002.
PDF
-
Seongmoo Heo and Krste Asanović,
"Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage
Reduction", VLSI Circuits Symposium,
Honolulu, HI, June 2002.
PDF
-
Krste Asanović, John Hennessy, David A. Patterson,
"Vector Processors", Appendix G in
Computer Architecture: A
Quantitative Approach, Third Edition,
Morgan Kaufman, ISBN 1-55860-596-7, May 2002.
PDF
-
Krste Asanović, Mark Hampton, Ronny Krashinsky, Emmett Witchel,
"Energy-Exposed Instruction Sets", in
Power Aware Computing,
Robert Graybill and Rami Melhem (Eds.),
Kluwer Academic/Plenum Publishers, ISBN 0-306-46786-0, May 2002.
PDF
-
Seongmoo Heo, Kenneth C. Barr, Mark Hampton, and Krste Asanović,
"Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bitlines",
29th International Symposium on Computer Architecture
(ISCA-29), Anchorage, AK, May 2002.
PDF
-
Albert Ma and Krste Asanović,
"A Double-Pulsed Set-Conditional-Reset Flip-Flop",
MIT LCS Technical Report, MIT-LCS-TR-844, May 2002.
PDF
- Theses Supervised:
-
Heidi Pan, "High-Performance Variable-Length Instruction Encodings"
M.Eng. Thesis, Massachusetts Institute of Technology, May 2002.
PDF
Winner, Charles and Jennifer Johnson Award for best
M.Eng. thesis in computer science, MIT, 2002.
-
Kenneth C. Barr, "Energy Aware Lossless Data Compression"
S.M. Thesis, Massachusetts Institute of Technology, September 2002.
PDF
2001
-
Krste Asanović,
"Vector Computing", in
The
Computer Engineering Handbook,
2nd Edition, Vojin Oklobdzija (Ed.), CRC Press, ISBN 0849308852,
December 2001.
-
Emmett Witchel, Sam Larsen, C. Scott Ananian, and Krste Asanović,
"Direct Addressed Caches for Reduced Power Consumption",
34th International Symposium on Microarchitecture (MICRO-34),
Austin, TX, December 2001.
PDF
-
Heidi Pan and Krste Asanović,
"Heads and Tails: A Variable-Length Instruction Format Supporting
Parallel Fetch and Decode",
International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems (CASES 2001), Atlanta, GA,
November 2001.
PDF
-
Michael Sung, Ronny Krashinsky, and Krste Asanović,
"Multithreading Decoupled Architectures for Complexity-Effective
General Purpose Computing",
Workshop on Memory Access Decoupled Architectures
(MEDEA'01), at International Conference on Parallel Architectures and
Compilation Techniques (PACT'01), Barcelona, Spain, September 2001.
PDF
-
Emmett Witchel and Krste Asanović,
"The Span Cache: Software Controlled Tag Checks and Cache Line Size",
Workshop on Complexity-Effective Design, at 28th International Symposium on
Computer Architecture (ISCA-28), Goteborg, Sweden, June 2001.
PDF
- Albert Ma, Michael Zhang, and Krste Asanović,
"Way Memoization to Reduce Fetch Energy in Instruction Caches",
Workshop on Complexity-Effective Design, at 28th International Symposium on
Computer Architecture (ISCA-28), Goteborg, Sweden, June 2001.
PDF
- Seongmoo Heo and Krste Asanović,
"Load-Sensitive Flip-Flop Characterization",
IEEE Workshop on VLSI, Orlando, FL, April 2001.
PDF
- Seongmoo Heo, Ronny Krashinsky, and Krste Asanović,
"Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy",
19th Conference on Advanced Research in VLSI (ARVLSI 2001), Salt
Lake City, UT, March 2001.
PDF
- Theses Supervised:
-
Mark Hampton, "Exposing Datapath Elements to Reduce Microprocessor
Energy Consumption"
S.M. Thesis, Massachusetts Institute of
Technology, June 2001.
PDF
-
Ronny Krashinsky,
"Microprocessor Energy Characterization and Optimization through Fast,
Accurate, and Flexible Simulation"
S.M. Thesis, Massachusetts
Institute of Technology, May 2001.
PDF
2000
- Michael Zhang and Krste Asanović,
"Highly-Associative Caches for Low-Power Processors",
Kool Chips Workshop, at 33rd International Symposium on
Microarchitecture (MICRO-33), Monterey,
CA, December 2000.
PDF
- Luis Villa, Michael Zhang, and Krste Asanović,
"Dynamic Zero Compression for Cache Energy Reduction",
33rd International Symposium on Microarchitecture (MICRO-33), Monterey, CA, December 2000.
PDF
- Jessica H. Tseng and Krste Asanović,
"Energy-Efficient Register Access",
SBCCI2000, XIII Symposium on Integrated Circuits and System
Design,
Manaus, Amazonas, Brazil, September 2000.
PDF
- Ronny Krashinsky, Seongmoo Heo, Michael Zhang, and Krste Asanović,
"SyCHOSys: Compiled Energy-Performance Cycle Simulation",
Workshop on Complexity-Effective Design, at 27th International
Symposium on Computer Architecture (ISCA-27), June 2000.
PDF
- Krste Asanović, "Energy-Exposed Instruction Set Architectures",
Work In Progress Session, Sixth International Symposium on High
Performance Computer Architecture (HPCA-6), Toulouse, France, January
2000. Published in IEEE TCCA newsletter, June 2000. PDF
- Theses Supervised:
-
Seongmoo Heo, "A Low-power 32-bit Datapath Design"
S.M. Thesis, Massachusetts Institute of Technology, August 2000.
PDF
-
Gong Ke Shen,
"A Procedural Layout Library in Java"
M.Eng. Thesis, Massachusetts Institute of Technology, May 2000.
PDF
1999
- Theses Supervised:
-
Jessica H. Tseng, "Energy-Efficient Register File Design"
S.M. Thesis, Massachusetts Institute of Technology, December 1999.
PDF
-
Mukaya Panich, "Reducing Instruction Cache Energy Using Gated
Wordlines"
M.Eng. Thesis, Massachusetts Institute of Technology, August 1999.
(PDF files:
Cover,
Abstract,
Contents,
Text)
1998
-
Krste Asanović, James Beck, David Johnson, John Wawrzynek, Brian
E. D. Kingsbury, and Nelson Morgan, "Training Neural Networks with
Spert-II". Chapter 11 in
Parallel Architectures for Artificial Neural Networks: Paradigms and
Implementations,
N. Sundararajan and P. Saratchandran (Eds.), IEEE Computer Society
Press, ISBN 0-8186-8399-6, November 1998, pp 345-364.
-
Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel,
"The PHiPAC v1.0 Matrix-Multiply Distribution".
Listed as both ICSI technical report TR-98-035 and UCB CS technical
report UCB/CSD-98-1020, October 1998.
PDF
- Krste Asanović,
"A vector processing system with multi-operation run-time
reconfigurable pipelines", US Patent 5,805,875, granted September 1998.
PDF
- Krste Asanović,
"Vector Microprocessors",
Ph.D. Thesis, University
of California at Berkeley, May 1998. The thesis is also available as
technical report UCB/CSD-98-1014 from the Computer Science Division,
University of California at Berkeley, Berkeley, CA94720.
1997
- Philipp Faerber and Krste Asanović, "Parallel neural network
training on Multi-Spert", IEEE 3rd International Conference on
Algorithms and Architectures for Parallel Processing, Special
session on Parallel Algorithms and Architectures for Neural
Processing, Melbourne, Australia, December 1997.
Postscript,
PDF.
-
David Patterson, Krste Asanović, Aaron Brown, Richard Fromm, Jason
Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos Kozyrakis,
David Martin, Stylianos Perissakis, Randi Thomas, Noah Treuhaft, and
Katherine Yelick.
"Intelligent RAM (IRAM): the industrial setting, applications, and
architecture",
International Conference on Computer Design (ICCD'97),
Austin, Texas, 10-12 October 1997.
Postscript
PDF
-
Christoforos Kozyrakis, Stylianos Perissakis, David Patterson, Thomas
Anderson, Krste Asanović, Neal Cardwell, Richard Fromm, Jason Golbus,
Ben Gribstad, Kimberly
Keeton, Randi Thomas, Noah Treuhaft, and Kathy Yelick,
"Scalable processors in the billion-transistor era: IRAM",
IEEE Computer, September 1997.
PDF
-
Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel,
"Optimizing matrix multiply using PHiPAC:
a portable, high-performance, ANSI C coding methodology",
11th ACM International Conference on Supercomputing (ICS'97), July 1997.
PDF
-
Krste Asanović,
"A fast Kohonen net implementation for Spert-II",
IWANN''97, Lanzarote, Canary Islands, Spain, June 1997.
PDF
-
Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel,
"Using PHiPAC to speed error back-propagation learning",
International Conference on Acoustics, Speech, and
Signal Processing (ICASSP'97), Munich, Germany, April 1997,
Volume 5, pp4153-4157.
PDF
1996
- Krste Asanović and James Beck, "T0 Engineering Data",
Listed as both ICSI technical report, TR-96-057, and as UCB CS technical
report, UCB/CSD-97-931, December 1996.
PDF
- Krste Asanović and David Johnson, "Torrent Architecture
Manual",
Listed as both ICSI technical report, TR-96-056, and as UCB CS technical
report, UCB/CSD-97-930, December 1996.
PDF
-
Krste Asanović, Brian Kingsbury, Bertrand Irissou, James Beck, and
John Wawrzynek
"T0: A single-chip vector microprocessor with reconfigurable
pipelines", In Proceedings 22nd European Solid-State
Circuits Conference (ESSCIRC'96), Editor: H. Grunbacher, Editions
Frontieres, September, 1996, pp344-347.
Postscript,
PDF
- Jeff Bilmes, Krste Asanović, Jim Demmel, Dominic Lam, and Chee-Whye Chin
"Optimizing Matrix Multiply using PHiPAC: a Portable,
High-Performance, ANSI C Coding Methodology",
LAPACK Working Note 111, UTK Technical Report, UT-CS-96-326, August 1996.
PDF
-
John Wawrzynek, Krste Asanović, Brian Kingsbury, James Beck,
David Johnson, Nelson Morgan,
"Spert-II: A vector microprocessor system",
IEEE Computer,
29(3):79-86, March 1996.
PDF.
1995
- Krste Asanović, James Beck, Bertrand Irissou, Brian Kingsbury,
Nelson Morgan, and John Wawrzynek,
"The T0 vector microprocessor",
Proceedings HOT Chips VII, Stanford, CA, August 1995.
1994
- Krste Asanović, James Beck, Jerry Feldman, Nelson Morgan, and John
Wawrzynek,
"A supercomputer for neural
computation", Proceedings of the International Conference
on Neural Networks, volume 1, pages 5-9, June 1994.
PDF
1993
- Krste Asanović, Nelson Morgan, John Wawrzynek,
"Using Simulations of Reduced Precision Arithmetic to Design a
Neuro-Microprocessor",
Journal of VLSI Signal Processing, 6:33-44, June 1993.
-
John Wawrzynek, Krste Asanović, Nelson Morgan,
"The Design of a Neuro-Microprocessor",
IEEE Transactions on Neural Networks, 4(3), May 1993.
PDF
- Krste Asanović, James Beck, Jerry Feldman, Nelson Morgan, and John
Wawrzynek, "Development of a Connectionist Network Supercomputer",
Proceedings of the Third International Conference on
Microelectronics for Neural Networks, pp 253-262, April 1993. A version is
available as an ICSI Technical Report
TR-93-021.
1992
- Denis B. Howe and Krste Asanović,
"SPACE: Symbolic Processing in Associative Computing Elements",
VLSI for Neural Networks and Artificial Intelligence,
Editors: Jose G. Delgado-Frias and William R. Moore,
Plenum Press, 1994, pp 243-252.
From Proceedings 3rd International Workshop on VLSI for Artificial
Intelligence and Neural Networks, September 1992.
HTML,
Postscript,
PDF
- Krste Asanović, James Beck, Brian Kingsbury, Phil Kohn, Nelson
Morgan, and John Wawrzynek,
"SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network
Computations",
Application Specific Array Processors Conference (ASAP'92),
Berkeley, USA, August 1992, pp178-190.
A version of this paper is available as ICSI Technical Report
TR-91-072.
- Krste Asanović, Klaus Erik Schauser, David A. Patterson, and
Edward H. Frank, "Evaluation of a stall cache: An efficient restricted
on-chip instruction cache", Proceedings 25th Hawaii International
Conference on System Sciences pp 405-415, January 1992.
PDF
An expanded version of this paper is available as UCB Technical Report
UCB/CSD 91/641.
1991
- Krste Asanović and Nelson Morgan,
"Experimental Determination of Precision Requirements for
Back-Propagation Training of Artificial Neural Networks",
Proceedings 2nd International Conference on Microelectronics for
Neural Networks,
October 1991, Munich.
A version of this paper is available as ICSI Technical Report
TR-91-036.
1990
- Krste Asanović, Brian Kingsbury, Nelson Morgan, and John Wawrzynek,
"HiPNeT-1: A Highly Pipelined Architecture for Neural Network
Training", Proceedings IFIP Workshop on Silicon Architectures
for Neural Nets, pp 217-232, November 1990, St Paul de Vence,
France. A version of this paper is available as ICSI Technical Report
TR-91-035.
1988
- Krste Asanović and James R. Chapman,
"Spoken Natural Language as a Parallel Application",
Proceedings CONPAR88, volume B,
BCS Parallel Processing Specialist Group, September 1988.
Paper (text only) PDF.