Workshop on Software for Processor-In-Memory Based Parallel Systems (March 21 2004)


Co-Chairs: Mary Hall* and Hans P. Zima**

*USC Information Sciences Institute, Marina del Rey, CA
**JPL, Pasadena, CA and Institute for Software Science, University of Vienna, Austria

In conjunction with the Second Annual IEEE/ACM International Symposium on Code Generation and Optimization, Palo Alto, California, March 21, 2004


Processor-in-Memory (PIM) architectures avoid the von Neumann bottleneck in conventional machines by integrating high-density DRAM and CMOS logic on the same chip. Parallel systems based on this new technology are expected to provide higher scalability, adaptability, robustness, fault tolerance and lower power consumption than current MPPs or commodity clusters. A number of projects began exploring this technology over the past few years, including IRAM, HTMT, Terasys, Active Pages, DIVA, FlexRAM, Blue Gene BG/C and BG/L, PIM-Lite, and Gilgamesh.

This full-day workshop provides an overview of PIM technology from a software point of view and presents various approaches towards building a software infrastructure for PIM-based parallel systems, exploiting PIM for enhancing the performance of important applications, and exploring new algorithmic concepts enabled by PIM. These same software concepts, which focus on managing deep memory hierarchies, hiding memory latencies and co-locating computation and data, will be important to all scalable parallel systems of the future, even those not based on PIM technology.

In addition to the software issues, the workshop will touch on some of the architectural, technological and commercial issues in bringing PIM technology to fruition. The speakers of the workshop represent leading groups from academia, industry and government labs conducting research in this area.


TENTATIVE AGENDA



Last modified on Mar, 3, 2004.