The T0 Vector Microprocessor
T0 (Torrent-0) is a single-chip fixed-point vector microprocessor
designed for multimedia, human-interface, neural network, and other
digital signal processing tasks. T0 includes a MIPS-II compatible
32-bit integer RISC core, a 1KB instruction cache, a high performance
fixed-point vector coprocessor, a 128-bit wide external memory
interface, and a byte-serial host interface. Fabricated in a 1.0
micron CMOS process, the die measures 16.75mm square
and contains 730,701 transistors. At the maximum clock frequency of
45MHz, T0 can simultaneously sustain 720 million arithmetic operations
per second and 720MB/s of external memory bandwidth, with up to 30MB/s
of DMA I/O. The first use of T0 is as the core of the SPERT-II workstation accelerator board.
To learn more about T0 and SPERT-II, follow these links:
There is some further
local documentation only available from ICSI machines.
T0 was developed as part of the CNS-1 project in a collaboration between
researchers in the Computer Science Division of the
University of California at
Berkeley and the
Realization Group at the
International Computer Science Institute.
Primary support for this work was from ONR URI Grant N00014-92-J-1617,
ARPA contract number N0001493-C0249, NSF Grant No. MIP-9311980, and
NSF PYI Award No. MIP-8958568NSF.
David Johnson <davidj@ICSI.Berkeley.EDU>
$Date: 2002/02/25 20:22:35 $