SPERT-II: A Vector Microprocessor System

[Top of SPERT-II board]
Top of SPERT-II board.
 [Bottom of SPERT-II board]
Bottom of SPERT-II board.

SPERT-II is a double-slot SBus card for Sun-compatible workstations. The board is designed to accelerate neural network, human-interface, multimedia, and other digital signal processing tasks. SPERT-II contains a T0 vector microprocessor running at 40MHz, 8MB of 20ns SRAM, a Xilinx FPGA device for interfacing with the host, and various system support devices.

To learn more about T0 and SPERT-II, follow these links:

There is some further local documentation only available from ICSI machines.

SPERT-II was developed as part of the CNS-1 project in a collaboration between researchers in the Computer Science Division of the University of California at Berkeley and the Realization Group at the International Computer Science Institute.

Primary support for this work was from NSF Grant No. MIP-9311980, ONR URI Grant N00014-92-J-1617, ARPA contract number N0001493-C0249, and NSF PYI Award No. MIP-8958568NSF.

David Johnson <davidj@ICSI.Berkeley.EDU>
$Date: 2002/02/25 20:23:09 $