Torrent Vector Microprocessor Makes Debut

Micrograph of a T0 die.

The design of the Torrent architecture began in late 1992 when the idea of combining a vector execution unit with a RISC processor was first proposed by U.C. Berkeley Ph.D. candidate Krste Asanovic, who has worked with the Realization Group since 1989. From his earlier studies of how to customize processors to execute neural network algorithms efficiently, Asanovic concluded that a narrow "application-specific" approach would severely limit the flexibility that researchers typically require for their work. On the other hand, the general-purpose architecture of a conventional RISC processor would not offer a performance advantage over commercial workstations. Asanovic's solution, to incorporate both general and specific processing elements on a single silicon die, is the key feature of the Torrent design.

The first Torrent chip design, known internally at ICSI as T0 (T-Zero), implements this architecture in 1 micron CMOS with two metal layers on a 17 x 17 mm die. Included on the die are a MIPS-compatible scalar RISC processor, a vector coprocessor customized for compute-intensive tasks and a 1KB instruction cache. The vector unit features a vector register file containing 16 vector registers of 32 elements each, one vector memory pipeline, and two vector arithmetic pipelines. Each pipeline contains eight parallel datapaths, so it can produce up to eight results per cycle. Since the Torrent architecture specification is envisioned as a blueprint for a family of code-compatible processor chips, larger and faster devices can be designed later using more advanced silicon fabrication technology. All devices in the Torrent family will execute the same instruction set.

One particular task targeted for T0 is the popular back-propagation algorithm for training connectionist nets. Simulations indicate that T0 will be able to perform up to 50 million updates per second on this task for moderate-sized networks. This performance is somewhat higher than ICSI currently achieves using a four-board Ring Array Processor for the same problem (ICSI's Winter 1989 Newsletter featured an article on the RAP board).

The core design team that "realized" T0 include Asanovic, Brian Kingsbury and Bertrand Irissou, all students of U.C. Berkeley Computer Science Professor John Wawrzynek. Each team member contributed his unique experience to the project.

Brian, Krste and Morgan with the first T0 wafers.

John Wawrzynek with the first T0 wafers.

Micrograph of one full adder cell within the multiplier array.

Along the way, Irissou write utility programs for automatically routing wires and had responsibility for putting all the pieces together for the final design. He has since taken a position as a VLSI designer at Integration Associates in Mountain View, California.

Aside from his responsibilities as chief architect, Asanovic was in charge of the overall testing strategy. He was also the liaison with the software development effort, led by David Johnson (see page one for a profile of Johnson and his work on T0 and other ICSI projects).

Micrograph of the T0 logo.
The VLSI design team made sure their faces were etched onto every die!

To mark the end of the design phase, the three chip designers were honored at a Realization Group lunch on March 15. Krste Asanovic, Brian Kingsbury and Bertrand Irissou were presented with plaques marking their achievements. In addition, the de riguer project T-shirt was unveiled and modeled by the team.

Krste, Bertrand, and Brian model the Torrent T-shirt at the Realization Group picnic.

Krste, Bertrand, and Morgan at the Realization Group picnic.

Dr. Sassan Raissi, Prof. John Wawrzynek, and Krste Asanovic during the testing process.