Meeting Recorder: Portable Speech Recognition
Vector IRAM is a new chip architecture being developed at UC
Berkeley. It consists of a vector processor with embedded DRAM
on the same die. This provides very high bandwidth to memory,
as well as very high peak performance for vector code. Some
details can be found below. For more information, see the IRAM webpages.
High absolute performance
- Floating-point and integer vector units.
- High bandwidth access to memory.
High performance per watt
- Low instruction dispatch rate for vector code.
- On-chip memory reduces need to drive external pins.
Well-suited to Meeting Recorder application
- Signal processing and phone probability estimation components of the
speech recognition engine are easily
vectorized. Decoder component requires additional research.
- Streaming media benefits from on-chip memory architecture
(compared, for example, to traditional cache architecture).
- Low power, integrated, inexpensive, etc.
Easy software development
- Full support for floating-point.
- Simulators already exist that run on conventional hardware.
- C/C++/Fortran compiler based on Cray's vectorizing compiler.
[ Home Page | Data Collection | More on Speech Recognition ]